Our work on processor architectures resulted in the book "Processor Architecture - from dataflow to superscalar and beyond" published by Springer-Verlag, Berlin, New York. The book surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. In hardware/software co-design of hard real-time embedded systems, we have investigated optimization methods based on high-performance heuristics (i.e., Hopfield neural network, genetic algorithm). We have proposed approaches for solving the real-time executive's problems of partitioning and scheduling, which are also applicable to a wide range of complex optimization problems from our everyday life (e.g., the parameters estimation problem, the school/university timetabling problem). The research in high-level architectural synthesis has been focused on evolutionary scheduling/allocation algorithms. We developed an improved evolutionary Allocation-Based Scheduling algorithm for the purpose of scheduling and allocating the operations in high-level synthesis. The algorithm generated optimal solutions in selected case studies and is therefore very appropriate for use in high-level synthesis. Our research of optimisation methods for solving combinatorial optimisation problems involved an ant-colony optimisation, which is a relatively new metaheuristic technique. We have developed multilevel and hybrid algorithms and applied them to mesh partitioning, which is a common problem in different engineering applications. The algorithms outperform the classical k-METIS, p-METIS, Chaco, and JOSTLE algorithm. In collaboration with the Faculty of Electrical Engineering and Computer Science, University of Maribor, we contributed to the work on triangular mesh decimation and TriMeDec Tool and the results published in international journals. Our research in test and diagnosis of integrated circuits and systems encompassed various activities covering both digital and mixed-signal test areas. In the frame of PROTEUS project, in collaboration with LIRMM, Montpellier, we developed an experimental IEEE 1149.4 mixed-signal test chip with extended Analog Boundary Module (ABM) functionality. A core disconnect switch is introduced which allows system-wide functional reconfiguration and proves very useful in the implementation of enhanced mixed-signal functional tests. Another modification of ABM cell enables comparison of analog input signals to multiple voltage levels. This feature augments the diagnostic capability of interconnect test. In the area of oscillation based test we proposed test structures for different classes of active RC filters. We have extended the application of oscillation based test structures to stimulus generation in built-in self-test. We have also shown how the oscillation based test structures, originally implemented for a go-no-go test, can be used for thermal testing by introducing a temperature dependant component in the test structure.