A high precision linear optical scanner is described, combining an averaged optical sensors array with an appropriate 10 µm graduated scales on measurement – fix plate and Vernier sliced parallel scale on a reading plate, where the total distortion of the generated quadrature sinusoidal signals below -60 dB was achieved by distributing and mismatching optical edges over a number of sine wave periods within a number of Vernier scaled periods. All these helps to improve measurement and regulation precision within ASSC system, realized in L2-9304 applied project.
COBISS.SI-ID: 7747924
A flash interpolation circuit converts a pair of periodic and orthogonal sine-signals into a stream of periodic – phase shifted sinusoidal signals, the amplitudes of which can be combined to produce useful information about the peak amplitude of the input sine-signals, independently of the signal’s frequency. An interpolation factor of 4 is shown to be sufficient for measuring amplitudes with an accuracy of 5.8 %. The interpolator architecture has been designed, integrated, evaluated and analyzed. The ASIC is designed and processed in 0.35 µm CMOS technology.
COBISS.SI-ID: 7987796
One of the goals of the signal conditioning module is the elimination of the phase shift that differs from the 90 degrees. For the verification of the design effectiveness the precision phase shift measurement method on the SPICE level is needed. Our second goal was to measure the time-dependent ultra small phase shift in the circuit where the amplitude, frequency and DC offset were also varying with the time. The measurement algorithm should be implemented with the SPICE scripting language.
COBISS.SI-ID: 7579988
A flash interpolator circuit inherent amplitude measurement algorithm, AMM, is described. The proposed technique of amplitude measurement is suitable for automatic gain control, AGC, and the systems for automatic signal conditioning, where a flash interpolator is already a part of the integrated motion control system. The SoC ASIC for incremental optical encoders is designed and processed in 0.35 µm CMOS technology.
A design consideration and representative design examples for battery assisted ASIC systems are presented using standard 350 nm technology where ordinary and low threshold devices are available. A number of parts from ASSC has already been analysed. As the low power and low voltage LPLV system design is predominated by low power objectives, the overall leakage has been considered as a dominant issue. To demonstrate the importance of leakage current to ASIC performance, the most representative designs are analyzed with Spectre simulation program.
COBISS.SI-ID: 7930196