The paper discusses the design and optimization of a high precision analogue gain stage, used to precisely adjust the amplitude of a wide band signal, through digitally adjustable gain. The stage can adjust monotonously the gain for all gain steps. The paper compares the characteristics like spread of gains, silicon area, parasitic capacitances, speed, etc., of the conventional approach using string resistors approach with improved digitally adjustable R-2R resistor ladder configuration. The proposed R2R approach occupies, in principle, much smaller silicon area, but it is difficult to achieve monotonicity for many gain steps without digital calibration of the structure. Monte Carlo simulations are used to analyze both structures.
B.03 Paper at an international scientific conference
COBISS.SI-ID: 11862868Most ASIC’s demand signal conditioning sub-circuits to modify various signal parameters; one important parameter is the gain. This paper presents the implementation of the gain stage with digital gain adjustment, in the range from 0.9 to 1.1 in 128 equidistant monotonous steps. For robust design in terms of the fabrication process and harsh environment operation, a fully differential amplifier was designed in standard 0.18µm TSMC CMOS technology. Designed amplifier in combination with resistive network is presented together with simulation results including the parasitic capacitances.
B.03 Paper at an international scientific conference
COBISS.SI-ID: 12346708The work describes design, simulation, and implementation of class AB trans-conductance power amplifier for large capacitive loads in CMOS 0.18um technology. Different topologies of power stage are analyzed together with different compensation possibilities. Very thorough simulation analysis under different conditions was performed. The results revealed that it is possible to implement such amplifier and can drive up to 1nF capacitive load. Measured results are compared with simulation results and are mostly in agreement.
D.10 Educational activities
COBISS.SI-ID: 54312451The work deals with the design and implementation of low-noise circuit used for measurements of photo diodes in the array of photodiodes. All-important parasitic factors are taken into considerations and how they influence Measurement accuracy. The analysis of noise contributions is given in the work together with methods to reduce their influences to the results of the measurements.
D.10 Educational activities
COBISS.SI-ID: 12658260Drago Strle is a member of the Editorial Board of ESSCIRC: European Solid State Circuit Conference
C.01 Editorial board of a foreign/international collection of papers/book
COBISS.SI-ID: 7641428